Document Type

Conference Paper

Rights

Available under a Creative Commons Attribution Non-Commercial Share Alike 4.0 International Licence

Disciplines

2.2 ELECTRICAL, ELECTRONIC, INFORMATION ENGINEERING

Abstract

Performance of multilevel inverters (MLI) are distinguished because of their low harmonic waveform generation, low filtering requirements on AC side and high voltage application. Among different (MLI) topologies, cascaded multi-level inverters (CMLI) are easier to implement and are much more cost effective. The main drawback of multilevel inverters is requirement of more than one isolated DC source and a lot of switches which makes them bulky and expensive to implement. To address this issue, researchers have investigated new topologies with reduced number of switches compared to conventional multilevel converters. In this paper, a new grid-tied cascaded multi-level topology with reduced number of switches is proposed. Compared to a standard 11-level MLI, the number of switches are reduced. The objective of the design is to reduce the number of DC sources and switches in order to reach the same level of the output voltage. Finally, performance of the proposed topology with a range of modulation and load power factor, operation regarding connection to the grid with closed loop control and comparative study with the other topologies is presented.

DOI

https://doi.org/10.1109/UPEC.2017.8231983


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